1. Technical Field of the Invention
The present invention relates to a non-volatile memory device and a method of fabricating the same. More specifically, the present invention is directed to silicon-oxide-nitride-oxide-silicon (SONOS) memory device having a cell transistor for storing information in a stacked gate insulating layer and a method of fabricating the same.
2. Description of the Related Art
Non-volatile memory devices are typically classified as either floating gate type non-volatile memory devices such as a flash memory device or floating trap type non-volatile memory devices such as a SONOS memory device. The flash memory device stores charges (i.e., free carriers) in a floating gate, and the SONOS memory device stores charges in a trap that is spatially isolated in a charge storage layer.
When storing free carriers, a flash memory device may lose all charges stored in a floating gate due to a partial defect of a tunnel oxide layer. Therefore, the flash memory device needs a relatively thick tunnel oxide layer as compared to the SONOS memory device. As a thickness of the tunnel oxide layer is increased to enhance reliability, the memory device needs complex peripheral circuits based on a requirement for a high operating voltage. This requirement prevents a high integration state of devices from being achieved and increases power consumption.
On the other hand, a SONOS memory device may have a relatively thin tunnel oxide layer as compared to the flash memory device because charges are stored in a deep level trap. Therefore, a SONOS memory device is operable at low applied gate voltages of 5-10V.
A conventional NAND-type SONOS memory device constructs a cell array using an enhancement mode transistor whose threshold voltage has a positive value. Since the threshold voltage of the enhancement mode transistor has a positive value, a positive sense voltage must be applied to a gate electrode of the memory transistor when program/erase signals are sensed in a read operation. Accordingly, a circuit for generating the sense voltage is required. In a read operation, a positive sense voltage is applied to a gate of a selected cell and a positive read voltage is applied to gates of unselected cells, so that the NAND-type SONOS memory device turns on the selected cell. Because a threshold voltage of a transistor in a write state is above 5V, the read voltage should be higher than 7V. The unselected transistor in an erase state is soft-programmed by the high read voltage, causing the threshold voltage of the unselected transistor to be high as well.